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Micrel, Inc.
3.3V 28Mbps-2.5Gbps AnyRate(R) CLOCK AND DATA RECOVERY
SY87702L
SY87702L
FEATURES
3.3V power supply Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, OC-48*, and ATM Compatible with FDDI, Gigabit Ethernet, Fibre Channel, 2X Fibre Channel, SMPTE 259 and 292, and proprietary applications Low power Clock and data recovery from 28Mbps up to 2.5Gbps NRZ data stream Selectable reference frequencies via programmable multiplier Differential PECL and CML high-speed serial outputs Line receiver input: no external buffering needed Link fault indication 100K ECL compatible I/O Available in 64-Pin EP-TQFP package Product obsolete. Use SY87721L for new designs
DESCRIPTION
The SY87702L is a complete Clock Recovery and Data retiming integrated circuit for data rates from 28Mbps up to 2.5Gbps NRZ. The device is ideally suited for SONET/SDH/ ATM, Fibre Channel, and Gigabit Ethernet applications, as well as other high-speed data transmission applications. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. Onchip clock generation is performed through the use of a frequency multiplier PLL and can be used as a Clock Multiplier Unit (CMU). The integrated CMU can provide this clock signal at the TCLK outputs. Additionally, the TCLK output can be selected to provide a copy of the RCLK frequency. For SONET/SDH applications, the SY87702L includes a Link Fault Detection circuit. This circuit, enabled by the output of an optical module driving the CD input low, causes the recovery PLL of the SY87702L to lock to the reference clock's multiplied frequency under Loss-of-Signal conditions. This low jitter clock is provided at the RCLK outputs and is at the same frequency as that provided at the TCLK output.
*Meets OC-48 Jitter Tolerance and Transfer
APPLICATIONS
Transponders and section repeaters Multiplexer's: access, add drop (ADM), and terminal (TM) SONET/SDH/ATM: -based transmission systems, modules, and test equipment Terabit routers and broadband cross-connects Fibre optic test equipment HDTV switching and transmission
AnyRate(R) is a registered trademark of Micrel, Inc. M9999-072706 hbwhelp@micrel.com or (408) 955-1690
1
Rev.: D
Amendment: /0
Issue Date: July 2006
Micrel, Inc.
SY87702L
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
VCCO VCC GND GND RDIN+ RDIN- GND LFIN NC VCC
FREQSEL2 FREQSEL1
CD FREQSEL3
VCOSEL2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Part Number
48 47 46 45 44 43 42
Package Operating Type Range H64-1 H64-1 H64-1 H64-1 Industrial Industrial Industrial Industrial
Package Marking SY87702LHI SY87702LHI
Lead Finish Sn-Pb Sn-Pb
NC
VCOSEL1 PLLRN+ PLLRN- NC PLLRW+ PLLRW- NC VCCA GNDA PLLSW- PLLSW+ NC PLLSN- PLLSN+ NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND ENPECL RDOUTE+ RDOUTE- RDOUTC+ RDOUTC- VCCO RCLKE+ RCLKE- RCLKC+ RCLKC- VCCO TCLKE+ TCLKE- TCLKC+ TCLKC-
SY87702LHI SY87702LHITR(2) SY87702LHG(3) SY87702LHGTR(2, 3)
SY87702LHG with NiPdAu Pb-Free bar line indicator Pb-Free SY87702LHG with NiPdAu Pb-Free bar line indicator Pb-Free
64-Pin EPAD-TQFP
41 40 39 38 37 36 35 34 33
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
GND
DIVSEL3 DIVSEL2
REFCLK-
NC NC GND
GND CLKSEL
VCC
GND REFCLK+
64-Pin EPAD TQFP (H63-1)
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DIVSEL1 NC
NC
VCC
2
Micrel, Inc.
SY87702L
SYSTEM BLOCK DIAGRAM
TX Data Stream Optical Module RX Data Stream SY87702L CDR/CMU TXCLK SY877XXL Mux/Demux
Code Group Data (4, 5, 8, 10, Bits) Code Group Strobe
RX Clock
RX Data
Note: Add second SY877XXL for 16 or 20 bit parallel input and output.
Ref Sel CD Lock
Align
Carrier Detect
Serial EEPROM
SY877XXL Programmable Protocol Selector
SY877XXL Frame Detector
Code Group Rate Clock Alignment Detect
Reference Timing (8)
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Micrel, Inc.
SY87702L
FUNCTIONAL BLOCK DIAGRAM
PLLRW+
PLLRN+ PLLRN-
PLLRW-
NC*
RDOUTE+ RDIN+ RDIN- Phase Detector RDOUTC+ Charge Pump N/W RDOUTE-
Mux
VCO N/W1/W2/W3
RDOUTC- RCLKE+ RCLKE- RCLKC+ RCLKC-
Phase/ Frequency Detector
CD
Link Fault Detector
LFIN
REFCLK+ REFCLK- Phase/ Frequency Detector Charge Pump N/W
Mux
VCO N/W1/W2/W3
Divide by 1, 2, 4, 8, 10, 16, 20, 32
TCLKE+ TCLKE- TCLKC+ TCLKC-
FREQSEL3 FREQSEL2 FREQSEL1
DIVSEL3
DIVSEL2
DIVSEL1
VCOSEL2 VCOSEL1
PLLSW+
* Do not connect.
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PLLSW-
ENPECL
PLLSN+
PLLSN-
CLKSEL
Micrel, Inc.
SY87702L
FUNCTIONAL DESCRIPTION
Clock Recovery Clock Recovery, as shown in the block diagram, generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability, without incoming data, is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the multiplied frequency of the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30s data stream of continuous 1's or 0's for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE.
PIN NAMES
INPUTS RDIN [Serial Data Input] - Differential PECL This differential input accepts the receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of ten frequency ranges, or can be one of five specific frequencies, depending on the state of the FREQSEL and VCOSEL pins. The RDIN- pin has an internal 75K resistor tied to VCC. REFCLK [Reference Clock] - Differential PECL This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN input. The input frequency to REFCLK is limited to 325MHz or less, depending on the setting on the DIVSEL signals. The REFCLK- pin has an internal 75K resistor tied to VCC. CD [Carrier Detect] - PECL Input This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW, the data on the RDIN input will be internally forced to a constant LOW, the data output RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW, and the clock recovery PLL forced to lock onto the clock frequency generated from REFCLK. VCOSEL1, VCOSEL2 [VCO Select] - TTL Inputs These inputs select the VCO frequency range via either one of three wide-band PLLs, or a SONET/SDH specific narrow-band PLL. Only the selected PLL is enabled. All other PLL's are disabled. Please refer to Table 1.
VCOSEL1 0 0 1 1 VCOSEL2 0 1 0 1 Table. 1 Choice SONET/SDH 1.8 to 2.5GHz 1.25 to 1.8GHz 0.650 to 1.30GHz
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Micrel, Inc.
SY87702L
FREQSEL1, ..., FREQSEL3 [Frequency Select] - TTL Inputs These inputs select the output clock frequency range, as shown in Table 2. VCOCLK Divider 1 2
4 6 8 12 16 24
OUTPUTS LFIN [Link Fault Indicate] - O.C. TTL Output This output indicates the status of the input data stream RDIN. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (as per ALRSEL). LFIN is an asynchronous output. RDOUTE [Receive Data Out] - Differential PECL These ECL 100K outputs represent the recovered data from the input data stream (RDIN). This recovered data is sampled on the falling edge of RCLK. RDOUTC [Receive Data Out] - Differential CML This is the CML version of RDOUTE. RCLKE [Receive Clock Out] - Differential PECL These ECL 100K outputs represent the recovered clock used to sample the recovered data (RDOUT). RCLKC [Receive Clock Out] - Differential CML This is the CML version of RCLKE. TCLKE [Transmit Clock Out] - Differential PECL These ECL 100K outputs represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). TCLKC [Transmit Clock Out] - Differential CML This is the CML version of TCLKE. INPUTS/OUTPUTS PLLSN+, PLLSN- [Clock Synthesis Loop Filter] External loop filter pins for the clock synthesis narrowband PLL. PLLSW+, PLLSW- [Clock Synthesis Loop Filter] External loop filter pins for the clock synthesis wide-band PLLs. PLLRN+, PLLRN- [Clock Recovery Loop Filter] External loop filter pins for the clock recovery narrowband PLL. PLLRW+, PLLRW- [Clock Recovery Loop Filter] External loop filter pins for the clock recovery wide-band PLLs. OTHERS VCC VCCO VCCA GND GNDA NC Supply Voltage Output Supply Voltage Analog Supply Voltage Ground Analog Ground These pins are for factory test, and are to be left unconnected during normal use.
FREQSEL1 0 0
0 0 1 1 1 1
FREQSEL2 0 0
1 1 0 0 1 1
FREQSEL3 0 1
0 1 0 1 0 1
Table 2.
DIVSEL1, ..., DIVSEL3 [Divider Select] - TTL Inputs These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in Table 3. Please note that the divide by 32 selection, "011", is only available for use when FREQSEL are set to "000." REFCLK
DIVSEL1 0 0 0 0 1 1 1 1 DIVSEL2 0 0 1 1 0 0 1 1 Table 3. DIVSEL3 0 1 0 1 0 1 0 1 Multiplier 1 2 4 32 8 10 16 20
CLKSEL [Clock Select] - TTL Input This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. ENPECL [Enable PECL] - TTL Input This input, when HIGH (ENPECL = 1), enables the differential PECL outputs TCLKE RDOUTE, and RCLKE. It also disables the CML outputs, by setting TCLKC+, RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC-, RDOUTC-, and RCLKC- logic LOW. When set LOW (ENPECL = 0), this signal enables the differential CML outputs TCLKC, RDOUTC, and RCLKC. It also disables the PECL outputs by setting TCLKE+, RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE-, RDOUTE-, and RCLKE- logic LOW.
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Micrel, Inc.
SY87702L
DESCRIPTION
General The SY87702L is a complete clock and data recovery circuit, capable of dealing with NRZ data rates from 28Mbps through to 2.5Gbps. A reference PLL is used as a frequency synthesizer, both to multiply a clock to the desired transmit rate, and to train the recovery PLL in preparation for actual data recovery. VCO Selection SY87702L has four complete VCO circuits. Depending of the application and the frequency range, any one of these four perform data recovery. As indicated by the VCO selection table, there are three general purpose VCOs, covering one of three frequency ranges. However, to extend the range of the device, the output of the VCO may be divided down. In the case of the two highest frequency VCO, this divisor is always set to 1. For the lowest frequency VCO, the FREQSEL pins select which divisor, and hence, which range of frequencies the VCO will work over. In addition, for SONET/SDH applications, there is a narrow band, extremely low jitter PLL. It also uses the FREQSEL divisor to choose the correct SONET/SDH frequency. The various combinations of FREQSEL and VCOSEL are not arbitrary, but are limited to the subset shown in Table 4, where the range column indicates frequency in Mbps.
VCOSEL1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
VCOSEL2 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1
FREQSEL1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1
FREQSEL2 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 1
FREQSEL3 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1
Range (Mbps) 2488 (OC48) 1244 622 (OC12) 311 155 (OC3) 1800-2500 900-1250(1) 1250-1800 650-1300(2) 325-650(3) 163-325 109-216 82-162 55-108 41-81 28-54
Table 4.(4)
NOTES: 1. Suggested range for Fibre Channel applications. 2. REFCLK multiplier of 2 is not allowed in this range. 3. REFCLK multiplier of 1 is not allowed in this range. 4. Combinations of VCOSEL and FREQSEL other then those in this table result in undefined behavior, and should not be used.
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Micrel, Inc.
SY87702L
LOOP FILTER COMPONENTS(1)
CML OUTPUT DIAGRAM
VCC VCC
R1
C1
100
100
100
100 100
PLLSN+ or PLLSW+
R1 = 1.2k C1 = 1.0F (X7R Dielectric)
PLLSN- or PLLSW-
SY87702L
Figure 1. R1 Filter Component Figure 3. 50 Load CML Output
R2
C2
VCC
100
100 200
PLLRN+ or PLLRW+
R2 = 1.8k C2 = 1.0F (X7R Dielectric)
PLLRN- or PLLRW-
SY87702L
Figure 2. R2 Filter Component
NOTE: 1. Suggested Values. Values may vary for different applications.
Figure 4. 100 Load CML Output
TIMING WAVEFORMS
tCPWL REFCLK tDV RDOUT tODC RCLK
tCPWH
tDH
tODC
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Micrel, Inc.
SY87702L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VIN IOUT ICMLOUT Tstore TA Parameter Power Supply Voltage Input Voltage ECL Output Current CML Output Current Storage Temperature Range Operating Temperature Range -Continuous -Surge Rating -0.5 to +7.0 -0.5 to VCC 50 100 30 -65 to +150 -40 to +85 Unit V V mA mA C C
NOTE: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Min. 3.15 -- Typ. 3.3 400 Max. 3.45 -- Unit V mA Condition
100K PECL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VIH VIL IIL VOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input LOW Current Output HIGH Voltage Output LOW Voltage Min. VCC - 1.165 VCC - 1.810 0.5 VCC - 1.075 VCC - 1.860 Typ. -- -- -- -- -- Max. VCC - 0.880 VCC - 1.475 -- VCC - 0.830 VCC - 1.570 Unit V V A V V VIN = VIL(Min) 50 to VCC -2V 50 to VCC -2V Condition
CML DC ELECTRICAL CHARACTERISTICS(1)
VCC = VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Min. -- -- Typ. VCC - 0.025 VCC - 0.400 VCC - 0.200 Max. -- -- Unit V V 100 Environment 50 Environment Condition
NOTE: 1. Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in the 100 environment and a 200mV swing in the 50 environment. Refer to the "CML Output" diagram for more details.
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Micrel, Inc.
SY87702L
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VIH VIL IIH IIL IOLK VOL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output Leakage Current Output LOW Voltage Min. 2.0 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- Max. -- 0.8 +20 +100 -300 500 0.5 Unit V V A A A A V VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. VIN = 0.5V, VCC = Max. VOUT = VCC IOL = 4mA Condition
AC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol Parameter RCLK, TCLK Output Jitter(1) Min. -- 1000 -- 2.5 -- 1.2 1.2 -- 45 -- -- 100 100 Typ. -- -- 15 -- -- -- -- -- -- 200 65 -- -- Max. 0.010 -- -- -- 325 -- -- 1.0 55 300 120 -- -- Unit UI rms ppm s Gbps MHz ns ns ns % of UI ps ps ps ps 50 to VCC-2V No Load > 25% transition density Condition REFCLK Multiplier = 16
Lock Range/Training Range Acquisition Lock Time RDIN Maximum Data Rate REFCLK Maximum Frequency tCPWH tCPWL tIRF tODC tRE tFE tRC tFC tDV tDH REFCLK Pulse Width High REFCLK Pulse Width Low REFCLK Input Rise/Fall Time (20% to 80%) Output Duty Cycle (RCLK/TCLK) ECL Output Rise/Fall Time (20% to 80%) CML Output Rise/Fall Time (20% to 80%) Data Valid Data Hold
NOTE: 1. Except at OC-48.
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SY87702L
EVALUATION BOARD SCHEMATIC
L2 R48, 20 VCC R47, 130 S1
1 2 3 4 5 10 9 8 7 6
L1 VCCO
D1 D2
VCC HEADER 3X2 JP4
1 3 5 2 4 6
C3
C4
C2 D3 LED
C1 R17, 1.7k VCC
RDIN-: FORCE RDIN-: SENSE
RDIN+: FORCE RDIN+: SENSE
VCC VEE
VCC: PIN 58
VEE: PIN 57
VEE: PIN 56
VEE: PIN 59
NC: PIN 53
NC: PIN 52
SW DIP-5 VEE
VCC L3 VCCA R7 HEADER 6X2 JP1
1 3 5 7 9 11 2 4 6 8 10 12
R1, 5k
R2, 5k
R3, 5k
R4, 5k
R5, 5k
VCC R16, 5k JP2 GND 48 VEE: PIN 48 VEE RDOUTE+ RDOUTE- RDOUTC+ RDOUTC- VCCO: PIN 42 RCLKE+ RCLKE- RCLKC+ RCLKC- VCCO: PIN 37 TCLKE+ TCLKE- TCLKC+
64
63
62
61
60
59
58
57
56
55
53 NC 54 VCCO
52
51
50
49
RDIN+
RDIN-
LFIN
NC
VCC
GND
GND
VCC
GND
FREQSEL3
CD
FREQSEL2
FREQSEL1
VCOSEL2
1 C10 C5 R8 2 C41
VCOSEL1 PLLRN+
C9
ENPECL RDOUTE+ RDOUTE- RDOUTC+ RDOUTC- VCCO
47 46 45 44 43 42 41
3 PLLRN- 4 NC
C6 S3
1 2 3 4 5 6 12 11 10 9 8 7
5 PLLRW+ C42 6 PLLRW- 7 NC 8 VCCA 9 GNDA
SY87702L
RCLKE+
RCLKE- 40 RCLKC+ 39 RCLKC- 38 VCCO 37
R9
SW DIP-6 VEE
C7 R10
10 PLLSW- C43 11 PLLSW+ 12 NC 13 PLLSN- C44 14 PLLSN+ 15 NC 16 NC
NC 17
VCC
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R18, 5k
VEE
R46, 100 VEE:PIN 26
R19, 5k
R20, 5k
C18
R21, 5k
R22, 5k
R23, 5k
TCLKE+ 36 TCLKE- 35 TCLKC+ 34 TCLKC- 33
GND REFCLK+ REFCLK-
C8
DIVSEL3 20
DIVSEL2 19
DIVSEL1 18
CLKSEL
22
TCLKC-
GND
GND
GND
VCC
VCC
NC
NC
NC 21
23
24
25
26
27
28
29
30
31
32
L7 VEE
VEE:PIN 32
REFCLK-: FORCE REFCLK-: SENSE
REFCLK+: FORCE REFCLK+: SENSE
C17 S2
1 2 3 4 5 10 9 8 7 6
JP3
VEE:PIN 25
VEE:PIN 23
VCC:PIN 24
L4 VCC C11 C12
R15, 1.2k
R14, 1.2k
R13, 1.2k
R12, 1.2k
R11, 1.2k
SW DIP-5 VCC
VEE
11
Micrel, Inc.
SY87702L
EVALUATION BOARD I/O TERMINATION SCHEMES
TCLK OUTPUTS RCLK OUTPUTS RDOUT INPUTS RDIN INPUTS
VCC R36, 83 RDIN+:FORCE R37, 125 VEE C31
1 2
TCLKC- R26, 100 VCC
C19
1
J14
2
RCLKC- R25, 100 VCC
C23 J10
1 2
RDOUTC- R29, 100 VCC
C27
1 2
J6
J1
TCLKC+ R27, 100 VCC
C20
1 2
J13
RCLKC+ R24, 100 VCC
C24
1 2
J9
RDOUTC+ R28, 100 VCC
C28
1 2
J5
RDIN+: SENSE
C32
1 2
J2
VCC R38, 83
TCLKE- R30, 330 VEE C21
1 2
J12
RCLKE- R32, 330 VEE
C25
1 2
J8
RDOUTE+ R34, 330 VEE
C29
1 2
J4
RDIN-:FORCE R39, 125 VEE
C33
1 2
J17
TCLKE+ R31, 330 VEE
C22
1 2
J11
RCLKE+ R33, 330 VEE
C26
1 2
J7
RDOUTE+ R35, 330 VEE
C30
1 2
J3
RDIN-: SENSE
C34
1 2
J18
NOTES: 1. For AC coupling, include capacitors C19 thru C31, C33, C35 and C37. 2. If DC coupling, remove resistors R36 thru R43. 3. For 50 CML systems, include resistors R24-R29. 4. For 100 CML systems, see Figure 3.
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SY87702L
REFCLK INPUTS
VCC R40, 83 REFCLK+:FORCE R41, 125 VEE C35
1 2
NC (FUTURE REV. OUTPUT)
NC: PIN 52
C39
1
J21
2
VEE: PIN 59
C45 0.01F
J15
R44, DNI VEE
VCC: PIN 58
C46 0.01F C47 0.01F C48 0.01F C49 0.01F C50 0.01F C51 0.01F C52 0.01F C53 0.01F C54 0.01F C55 0.01F C56 0.01F
VEE: PIN 57
VEE: PIN 56
C36
1 2
REFCLK+: SENSE
J16
NC: PIN 53 R45, DNI VEE
C40
1 2
J22
VEE: PIN 48
VCCO: PIN 42
VCCO: PIN 37
VCC R42, 83 REFCLK-:FORCE R43, 125 VEE C37
1 2
VEE: PIN 32
J19
VEE: PIN 26
VEE: PIN 25
VCC: PIN 24
REFCLK-: SENSE
C38
1 2
VEE: PIN 23
J20
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Micrel, Inc.
SY87702L
64-PIN EPAD H QUAD FLATPACK (H64-1)
Rev. 02
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-072706 hbwhelp@micrel.com or (408) 955-1690
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